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Preliminary W6694 PASSIVE USB-ISDN S/T-CONTROLLER
W6694 USB Bus ISDN S/T-Controller Data Sheet
The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W6694-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice.
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
Table of Contents1. GENERAL DESCRIPTION ............................................................................................................ 4 2. FEATURES ................................................................................................................................... 4 ISDN .............................................................................................................................................. 4 USB ............................................................................................................................................... 4 Other Features............................................................................................................................... 4 3. PIN CONFIGURATION.................................................................................................................. 5 4. PIN DESCRIPTION ....................................................................................................................... 6 5. SYSTEM DIAGRAM AND APPLICATIONS................................................................................... 8 6. BLOCK DIAGRAM ........................................................................................................................ 9 7. FUNCTIONAL DESCRIPTIONS .................................................................................................... 9 7.1 USB Descriptions ..................................................................................................................... 9 7.1.1 Control-IN Transactions (Endpoint 0)............................................................................ 10 7.1.2 Control-OUT Transactions (Endpoint 0)........................................................................ 13 7.1.3 Bulk-OUT Transaction (Endpoint 1) .............................................................................. 13 7.1.4 Bulk-IN Transaction (Endpoint 2) .................................................................................. 14 7.1.5 Interrupt-IN Transaction (Endpoint 3)............................................................................ 14 7.1.6 Isochronous-OUT Transaction (Endpoint 4) .................................................................. 14 7.1.7 Isochronous-IN Transaction (Endpoint 5) ...................................................................... 16 7.1.8 Suspend and Resume .................................................................................................. 17 7.2 Configuration EEPROM ......................................................................................................... 17 8. REGISTER DESCRIPTIONS ....................................................................................................... 18 8.1 Interrupt Registers.................................................................................................................. 18 8.1.1 Interrupt Status Register ISTA Read_clear............................................................... 18 8.1.2 Layer 1 Command/Indication Register CIR Read ....................................................... 18 8.1.3 Monitor Channel Interrupt Status MOIR Read_clear................................................. 19 8.1.4 PIO Input Change Register PICR Read_clear .......................................................... 19 8.2 Chip and FIFO Control Registers............................................................................................ 19 8.2.1 Interrupt Mask Register IMASK Read/Write Address 00h.......................................... 19 8.2.2 Command Register 1 CMDR1 Write Address 01h.................................................... 20 8.2.3 Command Register 2 CMDR2 Write Address 02h.................................................... 21 8.2.4 Control Register CTL Read/Write Address 03h ...................................................... 21 8.2.5 Layer 1 Command/Indication Register CIX Read/Write Address 04h......................... 22 8.2.6 U-layer1 Ready Code L1_RC Read/Write Address 05h............................................. 22 8.3 GCI Mode Registers ............................................................................................................... 22 8.3.1 GCI Mode Command Register GCR Read/Write Address 06h ................................. 22 8.3.2 Monitor Channel Control Register MOCR Read/Write Address 07h........................... 23 8.3.3 Monitor Channel Receive Register MOR Read Address 08h .................................... 24 -2-
Preliminary W6694
8.3.4 Monitor Channel Transmit Register MOX Read/Write Address 09h ........................... 24 8.4 Programmable IO Registers ................................................................................................... 24 8.4.1 PIO Input Enable Register PIE Read/Write Address 0Ah ......................................... 24 8.4.2 PIO Output Register 1 PO1 Read/Write Address 0Bh ............................................. 24 8.4.3 PIO Output Register 2 PO2 Read/Write Address 0Ch ............................................. 25 8.4.4 PIO Data Register PDATA Read Address 0Dh........................................................ 25 8.5 B Channel Switch Registers ................................................................................................... 25 8.5.1 Layer1 B1 Receiver Select Register L1B1RS Read/Write Address 0Eh...................... 25 8.5.2 Layer1 B2 Receiver Select Register L1B2RS Read/Write Address 0Fh...................... 26 8.5.3 USB B1 Receiver Select Register USBB1RS Read/Write Address 10h ...................... 26 8.5.4 USB B2 Receiver Select Register USBB2RS Read/Write Address 11h ...................... 26 8.5.5 PCM1 Receiver Select Register PCM1RS Read/Write Address 12h.......................... 26 8.5.6 PCM2 Receiver Select Register PCM2RS Read/Write Address 13h.......................... 27 9. ELECTRICAL CHARACTERISTICS............................................................................................ 27 9.1 Absolute Maximum Rating ..................................................................................................... 27 9.2 Power Supply ......................................................................................................................... 28 9.3 DC Characteristics ................................................................................................................. 28 9.4 Preliminary Switching Characteristics..................................................................................... 30 9.4.1 PCM Interface Timing................................................................................................... 30 9.4.2 Serial EEPROM Timing................................................................................................ 31 10. ORDERING INFORMATION...................................................................................................... 32 11. PACKAGE INFORMATION ...................................................................................................... 33 48L LQFP (7 x 7 x 1.4 mm footprint 2.0 mm) ............................................................................... 33
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
1. GENERAL DESCRIPTION
The Winbond's single chip USB bus ISDN S/T interface controller W6694 is an all-in-one device suitable for ISDN Internet access. The integrated USB and ISDN design provides low cost, pure passive solution for USB-IDSN application. W6694 also provides two PCM CODEC interfaces for the ability to access ISDN through voice channel.
2. FEATURES
ISDN
* Full duplex 2B+D S/T-interface transceiver compatible with ITU-T I.430 Recommendation - Four wire operation - Received clock recovery - Layer 1 activation/deactivation procedure - D channel access control * Transparent data transmission of 2B+D channels * Test functions
USB
* USB Specification version 1.0/1.1 compliant * Full-speed, bus-powered USB device * Integrated transceiver, PLL, SIE, SIL and voltage regulator * Built-in fully automatic enumeration procedure * Support suspend mode - Suspend current requirement - Wake-up by ISDN (remote) and PC (host)
Other Features
* GCI bus interface (slave mode) for connecting to ISDN U transceiver chip. * PCM port provides two 64K clear channels to connect to PCM CODEC chips. * B channel data switching function for selective connection between ISDN/GCI interface, USB and PCM. * EEPROM interface for retrieving customized USB device identification data. * IO pins with LED current drive capability. * Reset pin for whole-chip reset.
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Preliminary W6694
3. PIN CONFIGURATION
V S S U
N C
S U S P
I O P 7
I O P 6
I O P 5
I O P 4
I O P 3
I O P 2
I O P 1
I O P 0
36 VDDU D+ DVDD3 UCLK1 UCLK2 VDD3I VSS1 SR1 SR2 VDD1 SX1 37 38 39 40 41 42 43 44 45 46 47 48 1
35
34
33
32
31
30
29
28
27
26
25 24 23 22 21 20 19 18 17 16 15 14 13 VDD23 VSS23 TEST2 TEST1 EPDO EPDI EPSK EPCS PRXD PTXD VDD22 VSS22
2
3
4
5
6
7
8
9
10
11
12
S X 2
X T A L 1
X T A L 2
V S S 2 1
V D D 2 1
G C I D C L
G C I F S C
G C I D D
G C I D U
P F C K 1
P F C K 2
P B C K
FIG.3.1 W6694 Pin Out
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
4. PIN DESCRIPTION Table 4.1 W6694 Pin Descriptions
SYMBOL PIN NO. I/O USB Bus D+ DUCLK1 UCLK2 38 39 41 42 I/O I/O I O USB D+ data line. USB D- data line. 24 MHz crystal/oscillator clock input. 24 MHz crystal clock output. Left unconnected if use oscillator. S/T bus receiver input (-). This is normal polarity. Reverse polarity is also OK. S/T bus receiver input (+). S/T bus transmitter output(+). S/T bus transmitter output(-). Crystal or Oscillator clock input. The clock frequency: 7.68 MHz 100 PPM. Crystal clock output. Left unconnected when using oscillator. GCI Bus GCIDCL GCIFSC GCIDD GCIDU PFCK1 PFCK2 PBCK PTXD PRXD 6 7 8 9 10 11 12 15 16 I I I O O O O O I GCI bus data clock 1.536 MHz. GCI bus frame synchronization clock. GCI bus data downstream. (input) GCI bus data upstream. (output) PCM Bus PCM port 1 frame synchronization signal with 8 KHz repetition rate and 8 bit pulse width PCM port 2 frame synchronization signal with 8 KHz repetition rate and 8 bit pulse width PCM bit clock of 1.536 MHz. PCM data output. PCM data input. FUNCTION
ISDN Signals and External Crystal SR1 SR2 SX1 SX2 XTAL1 XTAL2 45 46 48 1 2 3 I I O O I O
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Preliminary W6694
4. Pin Description, continued
SYMBOL
PIN NO.
I/O
FUNCTION
External Serial EEPROM Interface EPCS EPSK EPDI EPDO VDD1,VSS1 VDD21, VSS21 VDD22, VSS22 VDD23, VSS23 VDDU, VSSU VDD3 VDD3I IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 IOP6 IOP7 17 18 19 20 47, 44 5, 4 14, 13 24, 23 37, 36 40 43 26 27 28 29 30 31 32 33 25 21, 22 34 35 I O I I/O I/O I/O I/O I/O I/O I/O I/O Others RESET TEST1, TEST2 SUSP NC I I O External reset. Cause internal circuit reset. Internal 10k ohm pull-up is provided. Test mode enable. Connected to HIGH for normal operation. USB suspended. Active HIGH NC No connection. Internal pull-up is provided. USB core power (5V), Ground Regulator output (3.3V) Regulator input (3.3V) IO Pins IO pin capable of driving LED. O O I O I I Serial EEPROM chip select. Serial EEPROM data clock. Serial EEPROM data input Serial EEPROM data output ISDN S/T analog power (5V), Ground Digital power (5V), Ground
Power and Ground
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
5. SYSTEM DIAGRAM AND APPLICATIONS
Typical applications include:
VDD 2 24MXI D1 1N4148 R1 10K VDD
USB passive TA for data only service USB passive TA with one data plus one voice
C1 10pF 1 2 Y1 24MXO 150 1 J1 JP1 1 R2 24MHz 1 C2 10pF 2 GND
1
1
1
CB2 0.1uF 2 2
CB3 0.1uF 2
CB4 0.1uF 2
CB5 0.1uF GND
2 RESET1 TR_RST 1
+ C3 1uF
SUSPEND IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 RESETN
+ CB1 1uF
1
RESETN
U1 3.3V VDD USBDP USBDN 24MXI 24MXO GND SR1 SR2 VDD SX1 37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25
2
768MXI VSSU NC SUSPEND IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 RESET#
C4 33pF 1 2 Y2
3.3V C6 22UF +
SX2 XTAL1 XTAL2 VSS21 VDD21 GCIDCL GCIFSC GCIDD GCIDU PFCK1 PFCK2 PBCK
VDDU D+ DVDD3 UCLK1 UCLK2 VDD3I VSS1 SR1 SR2 VDD1 SX1
R3 24 23 22 21 20 19 18 17 16 15 14 13 VDD GND VDD VDD EPDO EPDI EPSK EPCS VDD VDD GND IOP0 IOP1 IOP2 768MXO 220 1
7.68MHz 1 C5 33pF 2 GND
VDD23 VSS23 TEST2# TEST1# EPDO EPDI EPSK EPCS PRXD PTXD VDD22 VSS22
IOP3
IOP4
IOP5
IOP6
1 2 3 4 5 6 7 8 9 10 11 12
W6694-QFP48 D2 LED D3 LED D4 LED D5 LED D6 LED D7 LED D8 LED D9 LED
USB1 BUS_P DD+ B_GND C 1 2 3 4 VDD USB_PUSB_P+ 6 GND 4 5 R6 USBCONN 5 JP2 1 2 3 4 HEADER 4 22 USBDP R5 1.5K ATACH1 SW DPDT 3 1 2 3.3V 22 R4 USBDN
SX2 768MXI 768MXO GND VDD GND GND VDD
U2 EPCS EPSK EPDO EPDI 1 2 3 4 CS SK DI DO VCC NC NC GND 8 7 6 5 VDD R15 560 R16 560 R17 560 R18 560 R19 560 R20 560 R21 560 R22 560
GND
NMC9346 DIP8
FB1 SX1 R7 18 D10 1N4148 D11 1N4148 D13 D14 D15 VDD VDD SX1C SX1A SX1C 1 2 3 4 5 6 8 9 1 2 3 4 5 6 8 9 18 17 16 15 14 13 11 10 18 17 16 15 14 13 11 10 SX2C 2 U3 FERRI BEAD JP3 JUMPER SR2C SR2A SX2A SX2C 1 1 2
D12
SR1C SR1A SX1A
1N4148
D16 1N4148
1N4148 D17 1N4148
1N4148
1N4148
ISDN1 R8 100 FB2 FERRI BEAD 1 2 FB3 1 2 3 4 5 6 7 8
SX2
R9 18
SX2A
UT28615
SR1
R10 1.8K D18 1N4148 GND D20 R13 1.8K 1N4148
R11 SR1A D19 8.2K 1N4148 VDD VDD
SR1C 2
1
2
FERRI BEAD JP4 JUMPER ISDN CONNECTOR
SR2
D21 1N4148 R14 8.2K
1
R12 100 FB4 SR2A SR2C 1 2
FERRI BEAD
W6694 WITH USB & ISDN INTERFACE W6694 DEMO BOARD-DATA ONLY Size Document Number 15.20X12.00 D:\..\W6694_DEMO\W6694_DEMO.DSN\W6694.SCH Date: Monday, May 29, 2000 Sheet 1 of 1
Fig. 5.1 USB Passive TA Orcad Schematic
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IOP7
Preliminary W6694
6. BLOCK DIAGRAM
S/T Interface
Serial Interfac B e GCI Control B
Buffer
USB Bus
GCI Bus
B
EEPROM Control
Serial EEPROM Interface
PCM Codec Interface
PCM Port Control
B Channel Switch
IO Port Control
IO Port
FIG 6.1 W6694 Block Diagram
7. FUNCTIONAL DESCRIPTIONS
7.1 USB Descriptions
TAble 7.1 W6694 all USB Endpoints END POINT 0 1 2 3 4 5 TYPE DIRECTION* MAX. PACKET SIZE (BYTES) Control Bulk Bulk Interrupt Isoch. Isoch. IN/OUT OUT IN IN OUT IN 8/8 8 8 5 (1+3) + (1+18) = 23 1+ (1+7) + (1+15) + (1+15) = 41
* Direction: IN - device to host, OUT - host to device
INTERNAL BUFFER TYPE AND SIZE (BYTES) 8, single port x 2 8, single port x 1 8, single port x 1 5, single port x 1 96, dual port x 1 96, dual port x 1
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
USB standard requests are supported by W6694, and W6694 will respond to requests according to USB specification revesion 1.1. These includes "CLEAR_FEATURE, GET_CONFIGURATION, GET_DESCRIPTOR, GET_INTERFACE, GET_STATUS, SET_ADDRESS, SET_CONFIGURATION, SET_DESCRIPTOR, SET_FEATURE, SET_INTERFACE". The "SYNC_FRAME" request is not supported.
7.1.1 Control-IN Transactions (Endpoint 0) 7.1.1.1 Get Device Descriptor OFFSET 0 1 2 4 5 6 7 8 10 12 14 15 16 17 FIELD bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize idVendor idProduct bcdDevice iManufacturer iProduct iSerialNumber bNumConfiguration SIZE 1 1 2 1 1 1 1 2 2 2 1 1 1 1 DEFAULT VALUE (HEX) 12 01 0110 FF 00 00 08 1046 6694 0100 00 01 00 01 UPDATED BY EEPROM
Yes * Yes * Yes *
* Note: Refer to EEPROM session for its layout of contents.
7.1.1.2 Get Configuration Descriptor OFFSET 0 1 2 4 5 6 7 8 FIELD bLength bDescriptorType wTotalLength bNumInterface bConfigurationValue iConfiguration bmAttributes MaxPower SIZE VALUE (HEX) REMARK Configuration Descriptor 1 09 1 02 2 003E 1 01 1 01 1 00 1 A0 1 32
62
Bus Powered, Remote Wakeup 100 mA
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Preliminary W6694
7.1.1.2 Get Configuration Descriptor, continued
OFFSET 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 6 0 1 2 3 4 6
FIELD bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval
SIZE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
VALUE (HEX) 09 04 00 00 00 FF 00 00 00 09 04 00 01 05 FF 00 00 00 07 05 01 02 0008
REMARK
Interface 0 Descriptor
Alternate Interface 0 Descriptor
Endpoint 1 Descriptor
OUT Bulk
1 00 Endpoint 2 Descriptor 1 1 1 1 2 1 07 05 82 02 0008 00 IN Bulk
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
7.1.1.2 Get Configuration Descriptor, continued
OFFSET 0 1 2 3 4 6 0 1 2 3 4 6 0 1 2 3 4 6
FIELD bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval
SIZE 1 1 1 1 2 1 1 1 1 1 2
VALUE (HEX) 07 05 83 03 0005 01 07 05 04 01 0017
REMARK
Endpoint 3 Descriptor
IN Interrupt
Endpoint 4 Descriptor
OUT Isochronous
1 01 Endpoint 5 Descriptor 1 1 1 1 2 1 07 05 85 01 0029 01 IN Isochronous
Note: After W6694 is successfully enumerated by the USB host, software must issue SET_INTERFACE request with alternate setting 1, to enable all endpoints. When in default state (alternate setting 0), only endpoint 0 is functioning.
7.1.1.3 Get String Descriptor 0 OFFSET 0 1 2 FIELD bLength bDescriptorType wLanguage ID SIZE 1 1 2 VALUE (HEX) 04 03 0409 DESCRIPTION
U.S. English
7.1.1.4 Get String Descriptor 1 (Product) OFFSET 0 1 2 FIELD bLength bDescriptorType bString SIZE (HEX) 1 1 16 VALUE (HEX) 18 03 "USB ISDN TA" STRING (UNICODE)
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Preliminary W6694
7.1.2 Control-OUT Transactions (Endpoint 0) 7.1.2.1 Device Clear Feature, Remote Wake-up BmRequestType 00H bRequest CLEAR_FEATURE wValue 1 wIndex 0 wLength 0 Data None
On received this request from host, W6694 will not detect the incoming ISDN broadcast message.
7.1.2.2 Device Set Feature, Remote Wake-up BmRequestType 00H bRequest SET_FEATURE wValue 1 wIndex 0 wLength 0 Data None
On received this request from host, W6694 will detect the incoming ISDN broadcast message. This is default setting.
7.1.2.3 Set Interface 0, Alternate Setting 0 bmRequestType 01H bRequest SET_INTERFACE wValue 0 wIndex 0 wLength 0 Data None
On received this request from host, all endpoints except endpoint 0 are disabled. Also the B1/B2 channel FIFOs are reset and disabled. This is default setting.
7.1.2.4 Set Interface 0, Alternate Setting 1 bmRequestType 01H bRequest SET_INTERFACE wValue 1 wIndex 0 wLength 0 Data None
On received this request from host, W6694 will enable the B1/B2 channel XFIFO and RFIFO.
7.1.3 Bulk-OUT Transaction (Endpoint 1) Bulk-OUT endpoint is used to write data to register or/and index which register to be read in following Bulk-IN transaction. A pare of two bytes (Address, Data) in Bulk-OUT data packet represents a read or write command on one register. A maximum of 8 bytes consist one Bulk-OUT transaction. W6694 perform the read/write commands following their order in the packet. Data packet for Bulk-OUT transaction: Offset 0 address 1 1 data1 2 address 2 3 data2 4 address 3 5 data3 6 address 4 7 data4
Address byte will indicate the read or write action to that register, by assigning highest order bit (bit 7) to 0 (read) or 1 (write). Publication Release Date: October 2000 Revision A1
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Preliminary W6694
Contents of address byte: Bit 7 0/1 Bit 7: Bit 4-0: 6 0 5 0 4 A4 3 A3 2 A2 1 A1 0 A0
0/1 = Read/Write Address offset of register.
The data byte is the write data (write operation) or 00h (read operation). 7.1.4 Bulk-IN Transaction (Endpoint 2) Bulk-IN endpoint is for retrieving register data of W6694. It returns the registers data that are requested by most recent Bulk-OUT data-read request. Inside the data packet, one register occupies nd 2 bytes. The first is register's offset address, the 2 byte is date. A maximum of 4 register data can be sent to host in one Bulk-IN packet. Offset 0 address 1 1 data1 2 address 2 3 data2 4 address 3 5 data3 6 address 4 7 data4
7.1.5 Interrupt-IN Transaction (Endpoint 3) Interrupt-IN endpoint is used to periodically poll device interrupt data. W6694 use this endpoint to report interrupt status of all interrupt sources. All four bytes data of interrupt registers will be sent to host if ISTA is not 0. If no interrupt is detected by W6694 when received Interrupt-IN token, A NAK token will return to the USB host. Data packet for Interrupt-IN transaction: Offset 0 ISTA 1 CIR 2 PICR 3 PDATA 4 MOIR
7.1.6 Isochronous-OUT Transaction (Endpoint 4) After power-on or hardware reset, all B and D channels transmit FIFO (XFIFO) are disabled. A disabled XFIFO can not receive data from USB. But the transmitter will automatically send inter frame time fill pattern (all 1's) to ISDN interface. The disabled XFIFO can be enabled by command XEN on each channel. An enabled XFIFO can receive data from USB, and send data to the USB host. Software decides the size of data to transmit depending on available XFIFO space, which is indicated by XFR flag carried by Isochronous-IN packet. When XFR is reported to host, it means that XFIFO has at least half of the total XFIFO size available for that channel. Each channel has its own XFIFO and status flags. If the incoming Isochronous-OUT packet is detected error, some action will be automatically taken for D and B channel XFIFO. For D channel, the XFIFO is reset and automatically enabled. For B channel, the XFIFO are not reset, and the data remained in XFIFO are still valid and will be transmitted to ISDN later. But the new incoming B channel data will be replaced by FFh, and stored - 14 -
Preliminary W6694
into XFIFO. The continuous FFh will later be transmitted to corresponding B channel of ISDN interface. This Isochronous-OUT packet error will be reported to host, by setting bit ISOE of Isochronous-IN packet to 1. D channel FIFO will recognize and only accept data within HDLC frame (including opening and closing flag), all other data outside HDLC frame are ignored and not stored in FIFO. B channel FIFO accept any data after it is enabled.
Note: Because B1 and B2 channel data are of the same length (B_LEN), both channels should be reset/enabled at the same time.
The packet format of Isochronous-OUT is as below: Bit 7 6 5 4
st
3
2
1 D_LEN1
0 D_LEN0
D_DATA (1 byte) nd D_DATA (2 byte) rd D_DATA (3 byte) B_LEN3 B1_DATA ... B2_DATA ... D_LEN1-0 D Channel Data Length
B_LEN2
B_LEN1
B_LEN0
These bits indicate the data length of the subsequent data for D channel. The typical value is 1 to 3, if D channel message is sending; or 0 if no message to send. Once the opening flag of D channel message is sent, W6694 will move the data in D-XFIFO to S interface at the rate of 16K bps. The software must carefully assign proper length for each packet, otherwise a D-XFIFO under-run or overflow condition may occur. The only valid data are HDLC frame, including opening and closing flag (7Eh), and bit-stuffed data in between. Note that software should transmit the first data byte as opening flag in byte (8-bits) boundary. Due to the nature of HDLC framing, the closing flag may not be in byte-boundary. Software should stuff the remaining bit positions (if any) with binary `1', to fill the last byte, unless the last byte is 7Eh. D_DATA D Channel Data
These are D channel data space, which always occupy 3 bytes in the packet. Software should put actual data length in D_LEN. If the data length D_LEN is less then 3, the remaining data bytes should be all FFh. B_LEN3-0 B Channel Data Length
These bits indicate the data length of subsequent data for each B channel. Once the B-XFIFO is enabled (CMDR2:BnXEN), the length should be from 7 to 9 bytes inclusively, otherwise a transmit FIFO under run or overflow condition may occur. If there is no data for B1/B2 channel, the length can be 0. Note that the two B channels have same data length, but can be reset and enabled separately.
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
B1_DATA B1 Channel Data
These are B1 channel data, the length is indicated by B_LEN. B2_DATA B2 Channel Data These are B2 channel data, the length is indicated by B_LEN. 7.1.7 Isochronous-IN Transaction (Endpoint 5) After power on or reset, all B and D channels receive FIFO (RFIFO) are disabled. A disabled RFIFO can not receive data from ISDN, and will always return zero-length data for Isochronous-IN transaction. RFIFO can only be enabled by command CMDR:REN. Once enabled, an IsochronousIN transaction can read data from RFIFO of that channel. The data packet also carries XFIFO status for that channel, and the most recent Isochronous-OUT packet error status (if error ever occurred). Note that since B1 and B2 channel output length is the same in Isochronous-OUT packet, the XFIFO status of B1/B2 channels are the same. The packet format of Isochronous-IN is as below: Bit 7 ISOE D_XFR 6 D_XCOL 5 D_XDOV 4 3 2 D_LEN2 1 D_LEN1 0 D_LEN0
B1_XFR
B1_XDOV
B1_XDUN
B2_XFR
B2_XDOV
B2_XDUN
D_XDUN D_RDOV D_DATA ... B1_RDOV B1_LEN3 B1_DATA ... B2_RDOV B2_LEN3 B2_DATA ...
B1_LEN2
B1_LEN1
B1_LEN0
B2_LEN2
B2_LEN1
B2_LEN0
ISOE
Isochronous-OUT Error This bit is set to indicate that the most recent received Isochronous-OUT packet has CRC error. This bit will remain set, until a CMDR1:CISOE clears it.
XCOL Transmit Collision (D channel only) This bit indicates a D channel collision on the S-bus has been detected. The data in D channel XFIFO will be automatically re-transmitted, until the whole HDLC frame are successfully transmitted. This bit will remain set, until software issue CMDR1:DXEN to clear this bit. XFR Transmit FIFO Ready It is set when XFIFO has at least half of the XFIFO size available for incoming USB data. XDUN Transmit Data Under-run The corresponding XFIFO has run out of data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN bit. - 16 -
Preliminary W6694
XDOV Transmit Data Overflow The corresponding XFIFO has overflow condition. Data in XFIFO are overwritten by incoming USB data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN bit. RDOV Receive Data Overflow The corresponding RFIFO has overflow condition. Data in RFIFO are overwritten by incoming ISDN data. When overflow condition occurred, the D and B channel RFIFO is reset and disabled for that channel. This bit is cleared when RFIFO is enabled by REN bit. 7.1.8 Suspend and Resume W6694 supports USB suspend and resume function as described in USB specification 1.1. When there is more than three millisecond period of inactivity on the USB, W6694 will automatically enter into a low-power suspend state. In this state, most of the ISDN and USB module will be powered off to consume minimum power. But the internal register values are preserved. Therefore it is recommended that the software perform necessary control to W6694 before power-down. The W6694 will leave suspend mode only when one of the two condition happens: host or device wake-up. A ISTA:WAKE bit will indicate to software which source the wake-up event is originated from. (i). Host-Initiated Wake-up The USB host may wake-up W6694 by sending traffic on USB. On detected this wake-up signal, W6694 will automatically resume to normal operation. (ii). Device Remote Wake-up In suspend mode, W6694 will ignore any ISDN traffic on S/T bus, except for incoming broadcast messages. When there is an incoming broadcast message from ISDN switch, such as SETUP message, W6694 will automatically wake-up, and signal the USB host that it has left suspend mode. The incoming SETUP message will be saved in D channel RFIFO. After returning from suspend mode, software should immediately read the RFIFO, and perform necessary operation as specified in ISDN protocol.
7.2 Configuration EEPROM
A 9346/93C46 type serial EEPROM can be used to store customized USB device configuration data. These configuration data will be read by W6694 after power on or reset, and sent to the USB host during enumeration. If EEPROM is not presented, or the first 16 bits in EEPROM is FFFFh, the default value in W6694 will be sent to the USB host instead. EEPROM wire connection: W6694 EEPROM
EPCS EPCS EPSK EPD O EPDI
Chip Select Serial Clock Data In Data Out
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
EEPROM Contents : Offse t 0 2 4 Size (Byte) 2 2 2 Contents 15 0 Vendor ID Device ID Device release number
8. REGISTER DESCRIPTIONS
8.1 Interrupt Registers
These registers will be read by Interrupt-IN packet only, so the USB host will periodically receive these data. These registers can not be read by Bulk-IN transfer. 8.1.1 Interrupt Status Register ISTA Read_clear
This register indicates interrupt occurred in various interrupt sources. This register is cleared automatically after it is read and successfully ACKed by the USB host. Values after reset: 00h
7 6 5 4 3 2 1 0
ICC ICC
MOC
PIOIC
0
0
0
0
0
Layer 1 Indication Code Change A change of value in the received indication code has been detected. The new code is in Layer 1 Command/Indication Register (CIR) register. Monitor Channel Status Change A change of value in the GCI mode Monitor Channel Interrupt Register (MOIR) has occurred.
MOC
PIOIC Programmable IO Port Input Signal Changed A change of value in at least one input IO pin is detected. The input IO pins that change value can be identified in PIO Input Change Register (PICR) register. 8.1.2 Layer 1 Command/Indication Register CIR Value after reset: 0Fh
7 6 5 4 3 2 1 0
Read
0
0
0
0
CIR3
CIR2
CIR1
CIR0
CIR3-0 Layer 1 Indication Code Value of the received layer 1 indication code for S/T interface. Note these bits have a buffer size of two. - 18 -
Preliminary W6694
Note: If S/T layer 1 function is disabled and GCI bus is enabled (GE = 1 in GCR register), CIR register is used to receive layer 1 indication code from U transceiver. In this case, the supported indication codes are: Indication Deactivation Confirmation Power-up Indication Symbol DC PU Code 1111 0111 Descriptions Idle code on GCI interface U transceiver power up
8.1.3 Monitor Channel Interrupt Status Value after reset: 00h
7 6 5 4 3
MOIR
Read_clear
2
1
0
0 MDR MER MDA MAB
0
0
0
MDR
MER
MDA
MAB
Monitor Channel Data Receive Monitor Channel End of Reception Monitor Channel Data Acknowledged Monitor Channel Data Abort
8.1.4 PIO Input Change Register Value after reset: 00h
7 6 5 4 3
PICR
Read_clear
2
1
0
P7 P7-0
P6
P5
P4
P3
P2
P1
P0
Indicator of IO Pin Input Status 0: This IO pin is either output pin, or did not change input value. 1: This IO pin changed value.
NOTE : Registers in sections 8.2 to 8.5 are written/read by Bulk-OUT/Bulk-IN transactions.
8.2 Chip and FIFO Control Registers
8.2.1 Interrupt Mask Register Value after reset: E1h
7 6 5 4 3 2 1 0
IMASK Read/Write
Address 00h
ICC
MOC
PIOIC
0
0
0
0
1
Setting `1' to each bits masks the corresponding interrupt sources in ISTA register.
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
8.2.2 Command Register 1 Value after reset: 00h
CMDR1 Write
Address 01h
Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no effect.
7 6 5 4 3 2 1 0
DXRST
DRRST
DXEN
DREN
SRST
CISOE
DLP
RLP
DXRST D Channel Transmitter Reset Setting this bit resets D channel transmitter, and clear transmit FIFO (XFIFO). The transmitter will immediately transmit inter frame time fill pattern (all 1's) to D channel in ISDN layer 1, but the XFIFO is disabled (not active). Software must issue DXEN to enable (activate) D channel XFIFO. After reset is done, this bit becomes 0. If this bit and other bits are set at the same time, the reset action will be performed first and completed, then other actions will follow. DRRST D Channel Receiver Reset Setting this bit resets D channels receiver, and clear receive FIFO (RFIFO). The D channels is disabled (not active). Software must issue DREN to enable (activate) D channel RFIFO, in order to receive D channel data from ISDN, and send data to USB. After reset is done, this bit becomes 0. If this bit and other bits are set at the same time, the reset action will be performed first and completed, then other actions will follow. DXEN D Channel Transmit FIFO Enable Setting this bit enables D channel transmit FIFO (XFIFO). After enabled, the D channel XFIFO will begin to receive D channel data from USB, and send data to ISDN. After enabled, this bit becomes 0. DREN D Channel Receive FIFO Enable Setting this bit enables D channel receive FIFO (RFIFO). After enabled, the D channel RFIFO will begin to receive D channel data from ISDN, and send data to USB. After enabled, this bit becomes 0. SRST Software Reset Setting this bit internally generates a software reset signal. The effect of this reset signal is equivalent to hardware reset pin, except that the USB circuit and all USB configured data are not reset. This bit must be set along, i.e., all other bits in this register must not set at the same time. This bit is not auto-clear, once this bit is set to `1', software must write `0' to this bit to exit from the reset mode. In the reset-mode the chip will not function properly. CISOE Clear Isochronous-OUT Error Setting this bit clears error indication bit ISOE of Isochronous-OUT error. This bit is carried by Isochronous-IN packet. After bits are cleared, this bit becomes 0. DLP Digital Loopback Setting this bit activates the digital loopback function. The transmitted digital 2B+D channels are looped to the received 2B+D channels. Note that after hardware reset, the internal clocks will turn off if the S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to enable loopback function. This bit remains set, until cleared by software reset (SRST).
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Preliminary W6694
RLP Remote Loopback Setting this bit activates the remote loopback function. The received 2B channels from the S interface are looped to the transmitted 2B channels of S/T interface. The D channel is not looped in this loopback function. This bit remains set, until cleared by software reset (SRST).
8.2.3 Command Register 2 Value after reset: 00h
CMDR2 Write
Address 02h
Bits in this register act similar to that of CMDR1 register, except that the effect is on B1 or B2 channel XFIFO/RFIFO, instead of on D channel XFIFO/RFIFO.
7 6 5 4 3 2 1 0
B1XRST B1XRST B1RRST B1XEN B1REN B2XRST B2RRST B2XEN B2REN
B1RRST
B1XEN
B1REN
B2XRST
B2RRST
B2XEN
B2REN
B1 Channel Transmitter Reset B1 Channel Receiver Reset B1 Channel Transmit FIFO Enable B1 Channel Receive FIFO Enable B2 Channel Transmitter Reset B2 Channel Receiver Reset B2 Channel Transmit FIFO Enable B2 Channel Receive FIFO Enable CTL Read/Write Address 03h
8.2.4 Control Register Value after reset: 00H 7 0 6 0 5 0 4 0
3 0
2 0
1 OPS1
0 OPS0
OPS1-0 Output Phase Delay Compensation Select1-0 These two bits select the output phase delay compensation. OPS1 0 0 1 1 OPS0 0 1 0 1 Effect No output phase delay compensation Output phase delay compensation 260 nS Output phase delay compensation 520 nS Output phase delay compensation 1040 nS
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
8.2.5 Layer 1 Command/Indication Register CIX Value after reset: 0Fh
7 6 5 4 3 2 1 0
Read/Write
Address 04h
0
0
0
0
CIX3
CIX2
CIX1
CIX0
CIX3-0 Layer 1 Command Code Value of the command code transmitted to layer 1. A read to this register returns the previous written value.
Note: If S/T layer 1 function is disabled and GCI bus is enabled (GE = 1 in GCR register), CIX register is used to issue layer 1 command code to U transceiver. In this case, the supported command code is: Command Activate Request Command Symbol AR Code 1000 Descriptions Activate request command
8.2.6 U-layer1 Ready Code Value after reset: 0Ch
7 6 5 4
L1_RC Read/Write
Address 05h
3
2
1
0
0
0
0
0
RC3
RC2
RC1
RC0
RC3-0 Ready Code When GCI bus is being enabled, these four programmable bits are allowed to program different Layer 1_Ready Code (AI: Activation Indication) by user. For example: Siemens PEB2091: AI = 1100, Motorola MC145572: AI = 1100.
8.3 GCI Mode Registers
8.3.1 GCI Mode Command Register Value after reset: 00h
7 6 5 4 3 2 1 0
GCR
Read/Write
Address 06h
MAC MAC
0
0
TLP
GRLP
SPU
PD
GE
Monitor Transmit Channel Active (Read Only) Data transmission is in progress in GCI mode Monitor channel. 0: The previous transmission has been terminated. Before starting a transmission, software should verify that the transmitter is inactive. 1: The previous transmission is in progress.
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Preliminary W6694
TLP
Test Loopback When set this bit both the GCIDU and GCIDD lines are internally connected together. The GCI mode loopback test function: GCIDU is internally connected with GCIDD, external input on GCIDD is ignored.
GRLP GCI Mode Remote Loopback Setting this bit to 1 activates the remote loopback function. The 2B+D channels data received from the GCI bus interface are looped to the transmitted channels. SPU PD SPU 0 Software Power Up Power Down PD 1 DESCRIPTION After U transceiver power down, W6694 will receive the indication DC (Deactivation Confirmation) from GCI bus and then software has to set SPU 0, PD 1 to acknowledge U transceiver, by pulling GCIDU line to HIGH. W6694 remains normal operation. Setting SPU 1, PD 0 will pull the GCI bus GCIDU line to LOW. This will enforce connected layer 1 devices (U transceiver) to deliver GCI bus clocking. After reception of the indication PU (Power Up indication) the reaction of the microprocessor should be: - To write an AR (Activate Request command) as C/I command code in the CIX register. - To reset the SPU bit and wait for the following ICC (indication code change) interrupt. Unused.
1 0
0 0
1 GE
1
GCI Mode Enable Setting this bit to 1 will enable the GCI bus interface. In the same time, the S/T layer 1 function is disabled.
8.3.2 Monitor Channel Control Register Value after reset: 00h
7 6 5 4 3
MOCR Read/Write
Address 07h
2
1
0
0 MRIE
0
0
0
MRIE
MRC
MXIE
MXC
Monitor Channel 0 Receive Interrupt Enable Monitor channel interrupt status MDR, MER generation is enabled (1) or masked (0).
MRC
MR Bit Control Determines the value of the MR bit:
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
0: MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRIE = 1). 1: MR internally controlled according to Monitor channel protocol. In addition, the MDR interrupt is enabled for all bytes according to the Monitor channel protocol (if MRIE = 1). MXIE Monitor Channel Transmit Interrupt Enable Monitor interrupt status MDA, MAB generation is enabled (1) or masked (0). MXC MX Bit Control Determines the value of the MX bit: 0: MX always 1. 1: MX internally controlled according to Monitor channel protocol.
8.3.3 Monitor Channel Receive Register Value after reset: FFh
7 6 5 4 3
MOR
Read
Address 08h
2
1
0
8.3.4 Monitor Channel Transmit Register Value after reset: FFh
7 6 5 4 3
MOX
Read/Write
Address 09h
2
1
0
8.4 Programmable IO Registers
8.4.1 PIO Input Enable Register Value after reset: 00h
7 6 5 4 3 2 1 0
PIE
Read/Write
Address 0Ah
IE7 IE7-0
IE6
IE5
IE4
IE3
IE2
IE1
IE0
Input Enable for IO Pin 7-0. Setting these bits enable corresponding IO pin to become input pin. Default is output pin.
8.4.2 PIO Output Register 1 Value after reset: FFh
7 6 5 4
PO1
Read/Write
Address 0Bh
3
2
1
0
OM3_1
OM3_0
OM2_1
OM2_0
OM1_1
OM1_0
OM0_1
OM0_0
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Preliminary W6694
OMn_1-0 Output Mode of IO Pin n (n = 3...0). Setting corresponding bits drive output pin with different output mode. Possible modes are: 00: always LOW 01: 0.5 second HIGH/LOW cycle 10: 1 second HIGH/LOW cycle 11: always HIGH These bits have no effect on input pin. The default value of this register makes pin PIO0 flash if ISDN clock is enabled.
8.4.3 PIO Output Register 2 Value after reset: FFh
7 6 5 4
PO2
Read/Write
Address 0Ch
3
2
1
0
OM7_1 OMn_1-0
OM7_0
OM6_1
OM6_0
OM5_1
OM5_0
OM4_1
OM4_0
Output Mode of IO Pin n (n = 7..4).
8.4.4 PIO Data Register Value after reset: 00h
7 6 5 4 3
PDATA Read
Address 0Dh
2
1
0
D7 D7-0
D6
D5
D4
D3
D2
D1
D0
Read Data of IO Pins 7-0 The corresponding bits are the present values of IO pins 7-0 (LOW=0, HIGH=1).
8.5 B Channel Switch Registers
8.5.1 Layer1 B1 Receiver Select Register Value after reset: 04h
7 6 5 4 3 2 1 0
L1B1RS
Read/Write
Address 0Eh
0
0
0
0
0
RS2
RS1
RS0
RS2-0 Receiver Select These bits select the source where layer 1 B1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 100 (4): receive from USB B1
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
8.5.2 Layer1 B2 Receiver Select Register Value after reset: 05h
7 6 5 4 3 2 1 0
L1B2RS
Read/Write
Address 0Fh
0
0
0
0
0
RS2
RS1
RS0
RS2-0 Receiver Select These bits select the source where layer 1 B2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 011 (3): receive from Layer1 B2 101 (5): receive from USB B2
8.5.3 USB B1 Receiver Select Register Value after reset: 02h
7 6 5 4 3
USBB1RS
Read/Write
Address 10h
2
1
0
0
0
0
0
0
RS2
RS1
RS0
RS2-0 Receiver Select These bits select the source where USB B1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 100 (4): receive from USB B1 8.5.4 USB B2 Receiver Select Register Value after reset: 03h
7 6 5 4 3 2 1 0
USBB2RS
Read/Write
Address 11h
0
0
0
0
0
RS2
RS1
RS0
RS2-0 Receiver Select These bits select the source where USB B2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 011 (3): receive from Layer1 B2 101 (5): receive from USB B2 8.5.5 PCM1 Receiver Select Register Value after reset: 00h
7 6 5 4 3 2 1 0
PCM1RS
Read/Write
Address 12h
0
0
0
0
EPCM
RS2
RS1
RS0
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Preliminary W6694
EPCM Enable PCM Transmit/Receive 0: Disable data transmit/receive to/from PCM port. The frame synchronization clock is held LOW. The bit synchronization clock is LOW if both PCM ports are disabled. 1: Enable data transmit/receive to/from PCM port. The frame synchronization clock is active. The bit synchronization clock is active. RS2-0 Receiver Select These bits select the source where PCM1 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 011 (3): receive from Layer1 B2 100 (4): receive from USB B1 101 (5): receive from USB B2 8.5.6 PCM2 Receiver Select Register Value after reset: 00h
7 6 5 4 3 2 1 0
PCM2RS
Read/Write
Address 13h
0
0
0
0
EPCM
RS2
RS1
RS0
EPCM Enable PCM Transmit/Receive 0: Disable data transmit/receive to/from PCM port. The frame synchronization clock is held LOW. The bit synchronization clock is held LOW if both PCM ports are disabled. 1: Enable data transmit/receive to/from PCM port. The frame synchronization clock is active. The bit synchronization clock is active. RS2-0 Receiver Select These bits select the source where PCM2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 010 (2): receive from Layer1 B1 011 (3): receive from Layer1 B2 100 (4): receive from USB B1 101 (5): receive from USB B2
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Rating
PARAMETER Voltage on Any Pin with Respect to Ground Ambient Temperature Under Bias Maximum Voltage on VDD SYMBOL VS TA VDD LIMIT VALUES -0.4 to VDD +0.4 0 to 70 6 UNIT V C V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
9.2 Power Supply
PARAMETER 5V Input Voltage 3.3V Regulator Output Analog Ground Digital Ground SYM. VDD VDD3 VSSA VSSD MIN. 4.75 TYP. 5.0 3.3 0 0 MAX. 5.25 UNIT V V V V REMARKS Pins VDD1, VDD21, VDD22, VDD23, VDDU Pins VDD3I, VDD3 Pins VSS1 Pins VSS21, VSS22, VSS23, VSSU
9.3 DC Characteristics
T A = 0 to 70 C; VDD = 5V 5 %, VSSA = 0 V, VSSD = 0 V
PARAMETER Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Power Supply Current: Suspended Power Supply Current: Activated Absolute Value of Output Pulse Amplitude (VSX2-VSX1) Transmitter Output Current Transmitter Output Impedence
SYM. VIL VIH VOL VOH ICC
MIN. -0.4 2.0
MAX. 0.8 VDD +0.4 0.4
UNIT V V V V mA
TEST CONDITIONS
REMARKS
IOL = 12 mA
2.4
VDD = 5V, S/T layer 1 in state "F3 Deactivated without clock", USB in suspended mode VDD = 5V, S/T layer 1 in state "F7 Activated", USB is configured and active RL = 50
1) 1)
ICC
mA
VX
2.03 2.10
2.31 2.39
V V
SX1, 2
RL = 400
IX RX
7.5 30 23
13.4
mA k
RL = 5.6
1)
SX1, 2 SX1, 2
Inactive or during binary ONE During binary ZERO (RL = 50 )
Note: 1) Due to the transformer, the load resistance seen by the circuit is four times RL.
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Preliminary W6694
Capacitances of ISDN Pins
T A = 25 C, VDD = 5 V 5%, VSSA = 0V, VSSD = 0V, fc = 1 MHz, unmeasured pins grounded.
PARAMETER Output Capacitance Against VSSA Input Capacitance Load Capacitance
SYMBOL COUT CIN CL
MIN.
MAX. 10 7 50
UNIT pF pF pF
REMARKS SX1, 2 SR1, 2 XTAL1, 2
Recommended Oscillator Circuits
CL XTAL1
External oscillator signal
XTAL1
7.68MHz
CL50pF XTAL2
or
N.C. XTAL2
CL
Crystal specifications PARAMETER Frequency Frequency Calibration Tolerance Load Capacitance Oscillator Mode CL SYMBOL f VALUES 7.680 Max. 100 Max. 50 Fundamental UNIT MHz ppm pF
Note: The load capacitance CL depends on the crystal specification. The typical values are 33 to 47 pF.
External ocsillator input (XTAL1) clock characteristics PARAMETER Duty cycle MIN. 1:2 MAX. 2:1
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
9.4 Preliminary Switching Characteristics
9.4.1 PCM Interface Timing
PBCK (1.536MHz) 24 CHs PFCK1 CH 1 PFCK2 CH 2
PTXD
Port 1 Port 1
Port 2
Port 1 Port 1
Port2
PRXD
Port 2
Port 2
Note 1: These drawings are not to scale. Note 2: The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are located at channel 1 and channel 2, each with a 8 x PBCK duration.
Detailed PCM timing
ta1 ta2 PBCK ta3 ta5
PFCK1 PFCK2
ta4 PTXD ta7 PRXD
ta6
ta8
- 30 -
Preliminary W6694
PARAMETER ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8
PARAMETER DESCRIPTIONS PBCK pulse high PBCK pulse low Frame clock asserted from PBCK PTXD data delay from PBCK Frame clock deasserted from PBCK PTXD hold time from PBCK PRXD setup time to PBCK PRXD hold time from PBCK
MIN. 195
NOMINAL 325 325
MAX. 455 20 20 20
REMARKS Unit = nS
10 20 10
Note: The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125 S), PBCK and PFCK1, PFCK2 may be adjusted by one local oscillator cycle (130 nS) in order to synchronize with S/T clock. This shift is made on the LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with jitter amplitude 260 nS (peak-to-peak) and jitter frequency about 2.67~4 KHz.
9.4.2 Serial EEPROM Timing
tb1 tb2
EPSK tb3 EPCS tb4 EPSDI tb4 A5 A4 ..... A1 tb5 A0 D15 tb3
tb6 tb7 D14 ....... D1 D0
PARAMETER tb1 tb2 tb3 tb4 tb5 tb6 tb7
PARAMETER DESCRIPTIONS EPSK low EPSK high EPCS output delay EPSD output delay EPSD tri-state delay EPSD input setup time EPSD input hold time
MIN. 2500 2500
MAX.
REMARKS Unit = nS
30 30 30 30 30
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Publication Release Date: October 2000 Revision A1
Preliminary W6694
10. ORDERING INFORMATION
PART NUMBER W6694CD PACKAGE TYPE 48-pin LQFP PRODUCTION FLOW Commercial, 0 C to +70 C
0
11. PACKAGE INFORMATION
48L LQFP (7 x 7 x 1.4 mm footprint 2.0 mm)
HD
D A A2 A1
36
25
37
24
HE E
48
13
1
e
b
12
c
SEATING PLANE Y
L1 L
Controlling dimension: Millimeters
Symbol
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.006 0.057 0.010 0.008 0.280 0.280 0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.004 0 7 0 0.10 7 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
A A1 A2 b c D E e HD HE L L1 Y 0
0.020 0.026 0.354 0.354 0.024 0.039 0.358 0.358 0.030
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Preliminary W6694
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
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Publication Release Date: October 2000 Revision A1

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